New Type of DRAM Could Accelerate AI
Capacitorless DRAM using oxide semiconductors could be built in 3D layers above a processor’s silicon.
The transistors in the capacitorless DRAM developed by U.S.-based researchers includes a tungsten-doped indium oxide (orange) semiconductor, palladium top and bottom gates (yellow), nickel source and drain electrodes (green) and hafnium oxide dielectrics (blue).
One of the biggest problems in computing today is the “memory wall”—the difference between processing time and the time it takes to shuttle data over to the processor from separate DRAM memory chips. The increasingly popularity of AI applications has only made that problem more pronounced, because the huge networks that find faces, understand speech, and recommend consumer goods rarely fit in a processor’s on-board.
The DRAM memory cells in your computer are made from a single transistor and a single capacitor each, a so-called 1T1C design. To write a bit to the cell, the transistor is turned on and charge is pushed into (1) or removed from (0) the capacitor. To read from it, the charge (if there is any) is withdrawn and measured. This system is superfast, cheap, and consumes little power, but it has some downsides. For one, reading the bit drains the capacitor, so reading means writing the bit back to memory. What’s more, even if you don’t read the bit, charge will eventually leak out of the capacitor through the transistor. So all the cells need to be periodically refreshed just to keep the data. In modern DRAM chips, that’s done every 64 milliseconds.
This new concept of DRAM will benefit the Automobile and AI sector and will also bring benefit to the packing and packaging materials market of which Nexteck Singapore Pte Ltd is the key supplier of precision cover tape and WLCSP carrier tape for DRAM and chips.
